1. Field of Invention
The present invention relates to buffers. More particularly, the present invention relates to buffers employing push-pull operation.
2. Discussion of Related Art
Buffers are well known in electronics. FIG. 1A is a schematic representation of one type of prior art buffer 100a, which is configured as a source follower. The buffer 100a includes a transistor M1, a transistor M2, and a load CL, which is illustrated as a capacitor. In the illustrated example, transistors M1 and M2 are NMOS transistors. A drain terminal of transistor M1 is connected to a voltage supply VDD, while a gate terminal of transistor M1 receives an input signal Vin. Transistor M2 is configured as a current source, and is biased by signal Vbn. An output signal Vout of buffer 100a is provided by a source terminal of transistor M1, which corresponds to a drain terminal of transistor M2. A load CL is also connected to this terminal. When input signal Vin transitions from a low to high state, output signal Vout is able to closely track signal Vin. However, the buffer 100a exhibits an inadequate negative slew rate, such that when input signal Vin transitions from a high state to a low state the output signal Vout is unable to accurately follow input signal Vin. This is due in part to the limited current which transistor M2 can sink. Another drawback of buffer 100a is that it may also exhibit high power consumption when input signal Vin is static.
FIG. 1B is a schematic representation of another prior art buffer 100b, referred to as a low swing push-pull buffer. The buffer 100b includes a transistor M1 and a transistor M2. Transistor M1 is an NMOS transistor and has a drain terminal connected to a voltage supply VDD. Transistor M2 is as a PMOS transistor and has a drain terminal connected to ground. A load CL is connected between a source terminal of transistor M1 and ground. Output signal Vout is provided by the source terminal of transistor M1. Buffer 100b operates by the push-pull method. A splitter 12 using a linear circuit is used to split the input signal Vin into two outputs to drive the gates of NMOS transistor M1 and PMOS transistor M2 to achieve the push-pull operation. The buffer 100b suffers from a headroom problem when used with a low voltage design, and specifically with a low value of VDD. The headroom problem can be caused by the fact that the threshold voltage of the MOS transistors can limit the ability of Vout to reach the value of Vin, the two values being different from each other by a value of the MOS transistor threshold voltage.
FIG. 1C is a schematic representation of another prior art buffer 100c, referred to as a high swing push-pull buffer. The buffer 100c includes a transistor M1 and a transistor M2. Transistor M1 is a PMOS transistor and has a source terminal connected to a voltage supply VDD. Transistor M2, which is an NMOS transistor, has a drain terminal connected to the drain terminal of transistor M1. The drain terminal of transistor M1 is also connected to a terminal of load CL. A second terminal of load CL is connected to ground. An input signal Vin is supplied to a splitter 12, which uses a linear circuit to produce two outputs to drive the gates of transistors M1 and M2. Drawbacks of the buffer 100c include the fact that it generates additional poles and does not always meet power consumption constraints. Furthermore, the design is complex and the buffer demonstrates poor high frequency response.
In general, design constraints considered when designing a buffer may include the ability of the buffer to drive a large load, the dynamic and static power consumption of the buffer, frequency response, the complexity of design and manufacture of the buffer, and/or other characteristics of the buffer structure and operation. The circuits described thus far do not optimally satisfy all design constraints in various applications.